This page will soon grow in content and contain information about the scope of this research track.
Mon 20 Oct (GMT-07:00) Tijuana, Baja California change
|08:30 - 08:35|
|08:35 - 09:05|
|09:05 - 09:35|
|09:35 - 09:50|
|09:50 - 10:00|
|10:30 - 10:45|
|10:45 - 11:00|
|11:00 - 11:30|
|11:30 - 12:00|
|13:30 - 14:00|
|14:00 - 14:30|
|14:30 - 15:00|
|15:30 - 16:40|
|16:40 - 17:00|
Call for Papers
Stencil computations describe an important computational pattern that appears in a large variety of applications, including image processing, physical simulation, and linear algebra solvers. Because of their importance and wide usage, much effort is devoted to optimizing these kinds of computations on hardware that ranges from the largest supercomputers to handheld devices such as smartphones. Though conceptually simple, these computations have been traditionally difficult for general compilers to optimize, due to their difficult-to-analyze dependence structure and because the computations span many domains, each with different requirements for optimization and different tradeoffs. Thus, much of the real-world code used for stencil computations is hand-optimized for a particular application on a particular piece of hardware.
In recent years, a number of efforts have tried to automatically optimize stencil computations using general compilers, code generators, domain-specific languages, run-time systems, just-in-time compilation, and other strategies. This workshop aims to bring together these efforts along with users of stencils that require optimization to further the state of the art and promote a variety of research strategies for this important domain. Topics of interest include, but are not limited to, the following:
- memory and computational characterization of stencil applications
- domain-specific optimizations, languages, and compilers for stencils
- polyhedral stencil optimization
- optimization of stencils for accelerators and other hardware
- parallel & distributed stencil optimization
- general compiler support for optimizing stencils
- code generation & auto-tuning for stencils
- static analysis, synthesis & verification of stencil computations
- high-level libraries & frameworks
- frameworks, languages, & optimizations for composing stencils
- multigrid & AMR-specific stencil optimizations
Submissions should be a maximum of 7 pages (not including references) in the ACM SIGPLAN format. Proceedings will be published in the ACM Digital Library.
7 September 2014 15 September 2014 11:59PM PDT (16 Sept 0700 GMT) Notification: 21 September 2014 Workshop: 20 October 2014 Final Submission for Accepted Papers: 30 October 2014
Submissions should be a maximum of 7 pages (not including references) in the ACM SIGPLAN format, with authors blinded. Use the default 9pt format.
Please submit papers here: https://easychair.org/conferences/?conf=wosc2014.
Shoaib Kamil, MIT CSAIL Saman Amarasinghe, MIT CSAIL P. Saday Sadayappan, Department of Computer Science and Engineering, Ohio State University
Matthias Christen, Universita della Svizzera Italiana David Keyes, King Abdullah University of Science and Technology (KAUST) Jonathan Ragan-Kelley, Stanford Brian Van Straalen, ANAG/Lawrence Berkeley National Laboratory Samuel Williams, Lawrence Berkeley National Laboratory